FailureMode
Light Induced Degradation (LID)
- ID
fm:light-induced-degradation
- IRI
https://solarlattice.org/kb/fm/light-induced-degradation
- Status
- active
- Also known as
- LID
- Category
- Modules
Light induced degradation is a loss of module power that happens when cells are first exposed to light. In crystalline silicon modules it is mostly caused by boron-oxygen defects. In crystalline modules it usually costs a few percent in the first days of sun, while amorphous silicon modules can lose much more over their first months. You will not see it on the module. It shows as lower output power, short-circuit current, open-circuit voltage and fill factor. Confirm it with IV tracing or flash testing, and compare stabilized results and early production against nameplate. EL and IR imaging can help. Severe cases can cause mismatch and hot spots that show up in an IR camera. If early losses look larger than expected, have an accredited lab confirm them and claim the missing power under the warranty. To prevent it, choose low-LID or gallium-doped cell technology, check the cell type in the bill of materials, and include initial stabilization losses in yield estimates.
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- sentence 6: support check: partial - Confirming underperformance with an accredited lab and claiming missing power are stated, but the trigger 'larger than expected' and the 'under the warranty' framing are not explicit.
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Claims
caused_by
c1 verified · fact
Sunlight exposure
Power drops during the initial stabilization period when the module is first exposed to light.
verified by: joshuahamsaverified on: 2026-10-16
c2 verified · fact
Boron-oxygen defects
Boron-oxygen complexes form in boron-doped cells, mostly Czochralski mono-Si with leftover oxygen. They trap charge carriers.
verified by: joshuahamsaverified on: 2026-10-16
affects
c3 verified · fact
Solar cell
Mostly affects p-type boron-doped mono and multi crystalline cells. n-type and Ga-doped cells are much less affected.
verified by: joshuahamsaverified on: 2026-10-16
presents_as
c4 drafted · lead
Reduced STC output power
Seen early in system life. It does not come with any visual defect.
c5 drafted · lead
Reduced short-circuit current
c6 verified · fact
Low module open-circuit voltage
verified by: joshuahamsaverified on: 2026-10-16
c7 verified · fact
Reduced fill factor
verified by: joshuahamsaverified on: 2026-10-16
c8 drafted · lead
Non-uniform EL pattern
A patchwork pattern in EL images that grows more uneven can sometimes show that degradation is under way.
c9 drafted · lead
Hotspot in IR image
Only for serious LID above 10%, seen mainly in early PERC cells made before LID was mitigated in manufacturing.
leads_to
c10 drafted · lead
Module Hotspot from Cell Damage
LID can cause mismatch between cells, which can trigger hot spots and speed up ageing.
detected_by
c11 drafted · lead
IV curve tracing
c12 drafted · lead
Electroluminescence imaging
c13 drafted · lead
Infrared thermography
c14 drafted · lead
Flash testing
Compare stabilized flash-test results with nameplate and with the degradation expected for the technology.
c15 drafted · lead
Performance monitoring
Compare early-life production trends with nameplate and technology-specific expectations.
c16 drafted · lead
Accredited laboratory testing
Use an accredited PV test laboratory to confirm the underperformance.
mitigated_by
c17 drafted · lead
Low-LID module selection
c18 drafted · lead
Initial degradation in yield model
Underestimating initial degradation directly affects energy yield predictions.
c19 drafted · lead
Gallium-doped cells
Using Ga instead of B as the dopant removes B-O complex formation. Residual B impurities can still cause some LID.
c20 verified · fact
In-line cell stabilization
verified by: joshuahamsaverified on: 2026-10-16review note: support check: partial - Passages say manufacturers adapted production to stabilise cells in-line, but this is described mainly for LeTID rather than clearly for LID.
c21 drafted · lead
Bill of materials verification
Check the cell type.
c22 drafted · lead
Power warranty verification
c23 drafted · lead
Warranty claim
Claim the missing power once underperformance is confirmed.
c24 drafted · lead
Contractual loss tolerance
typical_power_loss
c25 verified · fact
1–3 PERCENT
Conditions: Classic LID in crystalline silicon modules, occurring only in the first days of sun exposure
verified by: joshuahamsaverified on: 2026-10-19review note: reviewer 2026-10-17: the compiler-flagged conflict is a different technology (amorphous vs crystalline silicon), not disagreement
c26 drafted · lead
≤ 30 PERCENT
Conditions: Light soaking effect across all module technologies (upper bound)
review note: support check: partial - The 30% upper bound is stated, but the claim that it applies across all module technologies is not.
c27 verified · fact
10–30 PERCENT
Conditions: Amorphous silicon modules (Staebler-Wronski effect) within the first months outdoors
verified by: joshuahamsaverified on: 2026-10-16review note: reviewer: the compiler-flagged conflict is a different scenario or technology, not disagreement
c28 drafted · lead
≤ 10 PERCENT
Conditions: LeTID variant at elevated temperature, which can add to the LID loss
Referenced by
Data