Solar Lattice

DetectionMethod

PID susceptibility lab test

ID
method:pid-lab-test
IRI
https://solarlattice.org/kb/method/pid-lab-test
Status
active
Also known as
IEC 62804, IEC 62804-1, PID test, System Voltage Durability Qualification Test

The PID susceptibility lab test checks how sensitive a module is to Potential Induced Degradation (PID) by putting a high voltage on the shorted module leads while the outer surfaces of the module are grounded. In the chamber method the module is held at about 60°C and 85% relative humidity for 96 hours under its rated system voltage and polarity, and the humidity itself provides the path to ground. Another method grounds the module face with a conductive electrode such as metal foil, typically at 25°C for 168 hours. This method skips frame features like edge clips or rear rails that would slow PID in the field. Power is measured before and after the stress. A module that loses more than 5% fails, and modules that failed the 60°C test also degraded from PID outdoors. Testing for polarization-type PID (PID-p) calls for UV illumination through a transparent electrode. In bifacial PERC modules the loss shows up much more strongly when the rear side is flash tested. Leakage current can be logged during the test to check that it is stable, but it is a weak indicator of how much the module has degraded. Limits: the test has not been shown to match field behavior for SHJ modules, chamber temperature and humidity must be kept uniform, and long tests at 85°C can set off other degradation mechanisms.

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Claims

produces

c1 drafted · lead Power loss after stress test

STC power is measured before and after voltage-bias stress; IEC 62804-type tests use a 5% power degradation pass/fail criterion. For PID-p in bifacial PERC, flash testing from the rear shows much larger loss than from the front.

typical_power_loss

c2 verified · fact ≤ 10 PERCENT

Conditions: Bifacial glass/glass PERC modules with EVA under combined-accelerated stress testing with -1200 V bias during illumination; relative degradation when flash tested from the front at STC, attributed to PID-p on the rear

verified by: joshuahamsaverified on: 2026-10-20review note: support check: partial - Passage says 'almost 10%' under -1200 V combined stress flash tested from front, not 'up to 10%' as a typical value; also a field-like combined test.; possible conflict with c3 (same source; check the conditions)

c3 verified · fact ≥ 50 PERCENT

Conditions: Same combined-accelerated stress test of bifacial PERC glass/glass EVA modules with -1200 V bias; relative degradation when flash tested from the rear at STC

verified by: joshuahamsaverified on: 2026-10-20review note: possible conflict with c2 (same source; check the conditions)

Referenced by

Data